References for 'Quantum-Well Logic Using Self-Generated Potentials' [ABSTRACTS]
- A link to the Patent Family information is included within each patent abstract
References for 'Quantum-Well Logic Using Self-Generated Potentials' [ABSTRACTS]
| Patent Number: |
5,032,877
|
| Title: | Quantum-coupled Rom |
| Family: | Patent family and legal status for 5,032,877 |
| INPADOC Status: | Expired -EXPIRED DUE TO FAILURE TO PAY MAINTENANCE FEE Effective DATE 20030716 |
| Inventor(s): | Bate, Robert T. (Garland, TX) |
| Assignee: | Texas Instruments Incorporated |
| Publication Number: | 5032877 |
| Application Number: | 06/626808 |
| Abstract: | A read only memory whererin information is encoded in the pattern of coupling of column lines to changes of quantum-coupled wells linked by resonant tunneling, which constitute rows. it is not strictly necessary that each chain of quantum wells itself constitute one row, but the extremely close packing density of the quantum wells nevertheless permits a very high row density. |
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| Patent Number: |
4,969,018
|
| Title: | Quantum-well Logic Using Self-generated Potentials |
| Family: | Patent family and legal status for 4,969,018 |
| INPADOC Status: | Expired -EXPIRED DUE TO FAILURE TO PAY MAINTENANCE FEE Effective DATE 20021106 |
| Inventor(s): | Reed, Mark A. (Dallas, TX) |
| Assignee: | Texas Instruments Incorporated |
| Publication Number: | 4969018 |
| Application Number: | 06/626807 |
| Abstract: | A new kind of electronic logic circuit, wherein potential wells (e.g. islands of GaAs in an AlGaAs lattice) are made small enough that the energy levels of carriers within the wells are discretely quantized. This means that, when the bias between the wells is adjusted to align energy levels of the two wells, tunneling will occur very rapidly, whereas when the energy levels are not aligned, tunneling will be greatly reduced. In particular, the wells are optimized to have sharp enough resonant tunneling peaks that the change in potential caused by the difference between the number of carriers stored between two adjacent tunnel wells is itself enough to permit or preclude resonant tunneling. Thus, a tremendous variety of logic functions, including all primitive Boolean functions can be embodied in this logic. |
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| Patent Number: |
4,912,531
|
| Title: | Three-terminal Quantum Device |
| Family: | Patent family and legal status for 4,912,531 |
| INPADOC Status: | Expired |
| Inventor(s): | Reed, Mark A. (Dallas, TX), Bate, Robert T. (Garland, TX) |
| Assignee: | Texas Instruments Incorporated A Corp Of De |
| Publication Number: | 4912531 |
| Application Number: | 06/626551 |
| Abstract: | A three-terminal quantum well device, which functions somewhat analogously to an MOS transistor. That is, the three terminals of the device can generally be considered as source, gate, and drain. An output contact is connected by tunneling to a number of parallel chains of quantum wells, each well being small enough that the energy levels in the well are quantized discretely. In each of these chains of wells, the second well is coupled to a common second conductor, and the first well is electronically coupled to a common first conductor. |
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| Patent Number: |
4,620,206
|
| Title: | Semiconductor Device |
| Family: | Patent family and legal status for 4,620,206 |
| INPADOC Status: | Expired -EXPIRED DUE TO FAILURE TO PAY MAINTENANCE FEE Effective DATE 19981028 |
| Inventor(s): | Ohta, Kimihiro (Kashiwa, JP), Nakagawa, Tadashi (Sakura, JP), Kawai, Naoyuki (Yatabe, JP), Kojima, Takeshi (Kashiwa, JP), Kawashima, Mitsuo (Toride, JP) |
| Assignee: | Agency Of Industrial Science And Technology |
| Publication Number: | 4620206 |
| Application Number: | 06/578574 |
| Abstract: | A semiconductor device comprises a superlattice semiconductor portion having a plurality of pairs of superlattice semiconductor thin films for forming step differences of band edge energy. The pairs of the thin films are laminated such that parameters which determine the structure of the thin films are monotonically changed in the direction of the lamination of the thin films. Electrodes are disposed to apply an electric field across both ends of the superlattice semiconductor portion. The semiconductor device has a good negative resistance characteristic and a large design freedom of semiconductor device. |
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| Patent Number: |
4,599,728
|
| Title: | Multi-quantum Well Laser Emitting At 1.5 .mu.m |
| Family: | Patent family and legal status for 4,599,728 |
| INPADOC Status: | Expired |
| Inventor(s): | Alavi, Kambiz (North Plainfield, NJ), Cho, Alfred Y. (Summit, NJ), Pearsall, Thomas P. (Summit, NJ), Temkin, Henryk (New Providence, NJ) |
| Assignee: | Bell Telephone Laboratories, Incorporated |
| Publication Number: | 4599728 |
| Application Number: | 06/512232 |
| Abstract: | A multi-quantum well laser having a Ga.sub.0.47 In.sub.0.53 As/Al.sub.0.48 In.sub.0.52 As active region emitting at 1.55 .mu.m and well layers having a thickness less than 150 Angstroms. |
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| Patent Number: |
4,589,115
|
| Title: | Wavelength Tuning Of Quantum Well Heterostructure Lasers Using An External Grating |
| Family: | Patent family and legal status for 4,589,115 |
| INPADOC Status: | Expired |
| Inventor(s): | Burnham, Robert (Palo Alto, CA), Holonyak, Jr., Nick (Urbana, IL), Chung, Harlan F. (Daly City, CA) |
| Assignee: | Xerox Corporation, Stamford, Ct., An Ny Corp. |
| Publication Number: | 4589115 |
| Application Number: | 06/530555 |
| Abstract: | The method of and apparatus for tuning the wavelength using an external diffraction grating is accomplished with a quantum well injection laser wherein the range of operating wavelength selection is extended beyond the expectations of wavelength selection in fundamental emission spectrum of conventional bulk-crystal heterostructure lasers to include wavelength selection at the multiple carrier recombination transition energies possible in the conduction band sub-bands and valence band sub-bands present in quantum well heterostructures of single or multiple quantum well lasers. Quantum well heterostructure lasers have a unique advantage over previous tuned semiconductor lasers, as exemplified in the previously cited prior art, in that the active region of the quantum well laser can be bandfilled to well above the bulk crystal band edge at moderate current densities indicative of excellent candidates for broad band tuning through a wide range of the quantum well sub-bands of the quantum well structure. |
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| Patent Number: |
4,581,621
|
| Title: | Quantum Device Output Switch |
| Family: | Patent family and legal status for 4,581,621 |
| INPADOC Status: | Expired -EXPIRED DUE TO FAILURE TO PAY MAINTENANCE FEE Effective DATE 19980408 |
| Inventor(s): | Reed, Mark A. (Dallas, TX) |
| Assignee: | Texas Instruments Incorporated |
| Publication Number: | 4581621 |
| Application Number: | 06/626806 |
| Abstract: | Quantum-coupled devices, wherein at least two closely adjacent potential wells, (e.g. islands of GaAs in an AlGaAs lattice) are made small enough that the energy levels of carriers within the wells are discretely quantized. This means that, when the bias between the wells is adjusted to align energy levels of the two wells, tunneling will occur very rapidly, whereas when energy levels are not aligned, tunneling will be greatly reduced. To provide output coupling from these quantum-well devices to macroscopic currents, the output from the quantum-well devices is injected into localized states close to an extremely small metal line (e.g. 200 Angstroms square in section). These trapped charged perturb the resistance of a metal line significantly, so that a conventional sense amplifier can be used for differential sensing between two such narrow metal lines, to provide macroscopic outputs. |
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| Patent Number: |
4,575,924
|
| Title: | Process For Fabricating Quantum-well Devices Utilizing Etch And Refill Techniques |
| Family: | Patent family and legal status for 4,575,924 |
| INPADOC Status: | Expired -EXPIRED DUE TO FAILURE TO PAY MAINTENANCE FEE Effective DATE 19980318 |
| Inventor(s): | Reed, Mark A. (Dallas, TX), Bate, Robert T. (Garland, TX) |
| Assignee: | Texas Instruments Incorporated |
| Publication Number: | 4575924 |
| Application Number: | 06/626809 |
| Abstract: | The present invention teaches a process for fabrication of quantum-well devices, in which the quantum-wells are configured as small islands of GaAs in an AlGaAs matrix. Typically these islands are roughly cubic, with dimensions of about 100 Angstroms per side. To fabricate these, an n- on n+ epitaxial GaAs structure is grown, and then is etched to an e-beam defined patterned twice, and AlGaAs is epitaxially regrown each time. This defines the quantum wells of GaAs in an AlGaAs matrix, and output contacts are then easily formed. |
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| Patent Number: |
4,532,535
|
| Title: | Electrically Reprogrammable Non Volatile Memory Cell Floating Gate Eeprom With Tunneling To Substrate Region |
| Family: | Patent family and legal status for 4,532,535 |
| INPADOC Status: | Expired |
| Inventor(s): | Gerber, Bernard (Neuchatel, CH), Fellrath, Jean (Neuchatel, CH) |
| Assignee: | Centre Electronique Horologer, S.A. (Neuchatel, CH) |
| Publication Number: | 4532535 |
| Application Number: | 06/408275 |
| Abstract: | An electrically erasable and reprogrammable non volatile memory cell is disclosed which is implemented in CMOS polycrystalline silicon gate transistor technology and comprises a p-channel MOS transistor the gate of which forms a first portion of a floating electrode. A second portion of said floating electrode has a substantially larger surface than the two other portions and is placed on a field oxide layer. A third portion of the floating electrode is placed on an injection oxide layer which is thinner than the gate oxide layer of the transistor. A p.sup.- -doped well is formed under said third portion and is connected electrically to a write control electrode. An erase control electrode is arranged opposite the second portion of the floating electrode. The disclosed memory cell can be erased and reprogrammed through relatively low control voltages of a single polarity and these processes lead only to very small current consumption. The control voltages can thus be produced by means of a voltage multiplier which can be integrated on the same substrate and be controlled by a battery constituting the voltage supply source of the memory. |
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| Patent Number: |
4,503,447
|
| Title: | Multi-dimensional Quantum Well Device |
| Family: | Patent family and legal status for 4,503,447 |
| INPADOC Status: | Expired |
| Inventor(s): | Iafrate, Gerald J. (Toms River, NJ), Aucoin, Thomas A. (Ocean, NJ), Ferry, David K. (Ft. Collins, CO) |
| Assignee: | Army, The United States Of America As Represented By The Secretary Of The |
| Publication Number: | 4503447 |
| Application Number: | 06/398740 |
| Abstract: | A superlattice semiconductor device consisting of a plurality of multi-dimensional charge carrier confinement regions of semiconductor material exhibiting relatively high charge carrier mobility and a low band gap which are laterally located in a single planar layer of semiconductor material exhibiting a relatively low charge carrier mobility and high band gap and wherein the confinement regions have sizes and mutual separation substantially equal to or less than the appropriate deBroglie wavelength. The device, in its preferred form, comprises a thin film of semiconductor material selected from group II-VI or III-V compounds or silicon wherein there is formed laterally located cylindrically shaped periodic regions which are adapted to act as quantum well confinement regions for electrons. |
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| Patent Number: |
4,439,782
|
| Title: | Semiconductor Device With Heterojunction Of Al.sub.x Ga.sub.1-x As--alas--g A |
| Family: | Patent family and legal status for 4,439,782 |
| INPADOC Status: | Expired |
| Inventor(s): | Holonyak, Jr., Nick (Urbana, IL) |
| Assignee: | University Of Illinois Foundation |
| Publication Number: | 4439782 |
| Application Number: | 06/209240 |
| Abstract: | The disclosure is directed to a semiconductor device comprising an active region between a pair of injecting/collecting layers, the active region comprising at least one layer of a first binary semiconductor material disposed between coupling barriers of a second different binary semiconductor material that is lattice matched to the first binary semiconductor material. In a preferred embodiment the active region comprises one or more layers of gallium arsenide separated by aluminum arsenide barrier layers. |
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| Patent Number: |
4,393,481
|
| Title: | Nonvolatile Static Random Access Memory System |
| Family: | Patent family and legal status for 4,393,481 |
| INPADOC Status: | Expired |
| Inventor(s): | Owen, William H. (Mountain View, CA), Simko, Richard T. (Los Altos, CA), Tchon, Wallace E. (Sunnyvale, CA) |
| Assignee: | Xicor Llc |
| Publication Number: | 4393481 |
| Application Number: | 06/209131 |
| Abstract: | Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems. |
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| Patent Number: |
4,389,612
|
| Title: | Apparatus For Reducing Low Frequency Noise In Dc Biased Squids |
| Family: | Patent family and legal status for 4,389,612 |
| INPADOC Status: | Expired |
| Inventor(s): | Simmonds, Michael B. (Del Mar, CA), Giffard, Robin P. (Palo Alto, CA) |
| Assignee: | S.h.e. Corportion |
| Publication Number: | 4389612 |
| Application Number: | 06/160225 |
| Abstract: | A circuit for reducing low frequency noise in a direct current biased superconducting quantum interference device. A squarewave bias signal having no dc component is used to bias the two junctions of the dc SQUID. At the same time, the magnetic flux in the SQUID is modulated to heterodyne the input signals up to some convenient frequency where they may be amplified without concern for drift. Final demodulation automatically adjusts for the fact that the relative phase is reversed each time the squarewave bias changes polarity states. |
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| Patent Number: |
4,353,081
|
| Title: | Graded Bandgap Rectifying Semiconductor Devices |
| Family: | Patent family and legal status for 4,353,081 |
| INPADOC Status: | Expired |
| Inventor(s): | Allyn, Christopher L. (Morristown, NJ), Gossard, Arthur C. (Warren, NJ), Wiegmann, William (Middlesex, NJ) |
| Assignee: | Bell Telephone Laboratories, Incorporated (Murray Hill, NJ) |
| Publication Number: | 4353081 |
| Application Number: | 06/116622 |
| Abstract: | A unipolar, rectifying semiconductor device is described. Rectification is produced by an asymmetric potential barrier created by a sawtooth-shaped composition profile of Al.sub.x Ga.sub.1-x As between layers of n-type GaAs. Single and multiple barriers, as well as doped and undoped barriers, show rectification. Also described is the incorporation of this type of device in an infrared detector, a hot electron transistor and mixer diodes. |
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| Patent Number: |
4,313,178
|
| Title: | Analog Solid State Memory |
| Family: | Patent family and legal status for 4,313,178 |
| INPADOC Status: | Expired |
| Inventor(s): | Stern, Ernest R. (Concord, MA), Ralston, Richard W. (Bedford, MA) |
| Assignee: | Massachusetts Institute of Technology (Cambridge, MA) |
| Publication Number: | 4313178 |
| Application Number: | 06/080099 |
| Abstract: | A solid state device capable of providing long-term storage of analog signals which in a particular embodiment utilizes a plurality of MNOS storage elements. An input analog signal is applied to a plurality of temporary storage means each associated with an MNOS storage element for temporarily storing a charge proportional to the amplitude of the portion of the input analog signal applied thereto. Storage control means are used to transfer the temporarily stored charges to the long-term MNOS storage elements so that controlled amounts of carrier charges are stored in the nitride layers thereof, such controlled amounts being substantially linearly proportional to the temporarily stored charges associated therewith. In a particular embodiment the input analog signal may be supplied via a surface acoustic wave (SAW) device and coupled to the MNOS device directly or it may be coupled to a charge-coupled device (CCD) and then coupled to the MNOS device. |
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| Patent Number: |
4,291,390
|
| Title: | Analog Solid State Memory |
| Family: | Patent family and legal status for 4,291,390 |
| INPADOC Status: | Expired |
| Inventor(s): | Stern, Ernest R. (Concord, MA), Ralston, Richard W. (Bedford, MA), Smythe, Jr., Daniel L. (Carlisle, MA), Burke, Barry E. (Lexington, MA) |
| Assignee: | Massachusetts Institute of Technology (Cambridge, MA) |
| Publication Number: | 4291390 |
| Application Number: | 06/080098 |
| Abstract: | A solid state device capable of providing long-term storage of analog signals which in a particular embodiment utilizes a plurality of MNOS storage elements. An input analog signal is applied to a plurality of temporary storage means each associated with an MNOS storage element for temporarily storing a charge proportional to the amplitude of the portion of the input analog signal applied thereto. Storage control means are used to transfer the temporarily stored charges to the long-term MNOS storage elements so that controlled amounts of carrier charges are stored in the nitride layers thereof, such controlled amounts being substantially linearly proportional to the temporarily stored charges associated therewith. In a particular embodiment the input analog signal may be supplied via a surface acoustic wave (SAW) device and coupled to the MNOS device directly or it may be coupled to a charge-coupled device (CCD) and thence coupled to the MNOS device. |
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| Patent Number: |
4,263,664
|
| Title: | Nonvolatile Static Random Access Memory System |
| Family: | Patent family and legal status for 4,263,664 |
| INPADOC Status: | Expired |
| Inventor(s): | Owen, William H. (Mountain View, CA), Simko, Richard T. (Los Altos, CA), Tchon, Wallace E. (Sunnyvale, CA) |
| Assignee: | Xicor Llc |
| Publication Number: | 4263664 |
| Application Number: | 06/071499 |
| Abstract: | Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems. |
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| Patent Number: |
4,051,393
|
| Title: | Current Switched Josephson Junction Memory And Logic Circuits |
| Family: | Patent family and legal status for 4,051,393 |
| INPADOC Status: | Expired |
| Inventor(s): | Fulton, Theodore Alan (Warren Township, Somerset, NJ) |
| Assignee: | Bell Telephone Laboratories, Incorporated (Murray Hill, NJ) |
| Publication Number: | 4051393 |
| Application Number: | 05/751127 |
| Abstract: | A superconductive circuit includes a loop circuit having first and second parallel branches connected in parallel with an appropriately terminated fan-out line. Each branch includes a Josephson junction device and the loop circuit includes at least one resistor. A bias current is applied directly to the loop circuit so that each Josephson device is biased below its critical current I.sub.J. A control current is then coupled (directly or inductively) to the loop circuit so that in one branch the bias and control currents add and exceed I.sub.J. The Josephson device in that branch switches from V = 0 to V = 2.DELTA. causing substantially the entire bias current to flow through the other branch and thereby switching the other Josephson device to V = 2.DELTA.. Now substantially all the bias current is diverted to the fan-out line which can be used to control other similar circuits, i.e., to provide either the control or bias current for other circuits. Logic is performed by using multiple control currents coupled to the loop circuit, a resistor in the fan-out line and preferably resistors in each branch. Memory is achieved by forming a totally superconductive closed circuit path including the fan-out line and a portion of the loop circuit. |
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| Patent Number: |
3,936,677
|
| Title: | Supercurrent Device For Controlling Mobile Flux Vortices |
| Family: | Patent family and legal status for 3,936,677 |
| INPADOC Status: | Expired |
| Inventor(s): | Fulton, Theodore Alan (Warren Township, Somerset County, NJ), Galt, John Kirtland (Albuquerque, NM) |
| Assignee: | Bell Telephone Laboratories, Incorporated (Murray Hill, NJ) |
| Publication Number: | 3936677 |
| Application Number: | 05/542712 |
| Abstract: | In an elongated weak-link supercurrent transmission line, the propagation of mobile flux vortices can be either enhanced or impeded by control means comprising a normal metal segment which interrupts either superconductor in the direction of vortex propagation and a control current source connected to the line at a point in operative relation to the normal metal segment. The control means either enhances or impedes the propagation of a vortex depending on the direction of the control current relative to that of the supercurrent associated with the vortex. The control means may also include a portion of the line in which its width is varied in order to change the velocity of the vortices. Also described is a switching device in which the transmission line is bifurcated and control means is located in each path to selectively block or transmit vortices, as well as a memory device in which the transmission line is formed in a closed loop and the normal metal segment serves to prevent the creation of anti-vortices in the loop. |
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| Patent Number: |
3,862,436
|
| Title: | Triangle Wave Generator Having Direct Tunnel Diode Switch Control |
| Family: | Patent family and legal status for 3,862,436 |
| INPADOC Status: | Expired |
| Inventor(s): | George, Richard E. (Anaheim, CA) |
| Assignee: | Interstate Electronics Corporation (Anaheim, CA) |
| Publication Number: | 3862436 |
| Application Number: | 05/426068 |
| Abstract: | A tunnel diode is used to directly drive a current switch for controlling the current supplied to the integrator of a triangle wave generator, a latching circuit being connected to maintain the current switch on the on or off state between successive driving signals from the tunnel diode. |
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| Patent Number: |
3,833,894
|
| Title: | Organic Memory Device |
| Family: | Patent family and legal status for 3,833,894 |
| INPADOC Status: | Expired |
| Inventor(s): | Aviram, Arieh (Yorktown Heights, NY), Seiden, Philip E. (Briarcliff Manor, NY) |
| Assignee: | International Business Machines Corporation (Armonk, NY) |
| Publication Number: | 3833894 |
| Application Number: | 05/371788 |
| Abstract: | The organic memory device described herein comprises an organic compound having a molecular structure which includes a mixed valence double well of an organic or organometallic redox couple separated by a .sigma., i.e., a non-conjugated bridge, the two components of the redox couple being the respective end groups of the structure. The remainder of the molecule is chosen to effect electro-neutrality. The total molecular structure is such that in a film of the compound laid down on a substrate surface, the molecules assume dispositions such that their long axes are substantially perpendicular to the plane of the surface. Examples of the redox couple are: ferrocene, ferrocenium .sym.; hydroquinone, quinone, tropylidine, tropylium.sym.; and dihydropyridine, pyridinium .sym.. This type of molecular structure exhibits a potential energy versus distance plot, wherein the term "distance" signifies the length of the molecule, i.e., from end group to end group of the redox couple, which defines first and second minimum potentials or wells separated by a maximum potential, the distance between the wells substantially corresponding to the length of the molecule. In operation, upon the application of a potential across a film of the compound, electrons are caused to tunnel from one minimum to the other to thereby define a given state. |
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| Patent Number: |
3,636,371
|
| Title: | Saw-tooth Voltage Wave Generator Including Ramp Voltage Source Controlled By Dual Stable State Tunnel-diode Switchable Periodically By A Gating Circuit |
| Family: | Patent family and legal status for 3,636,371 |
| INPADOC Status: | Expired |
| Inventor(s): | Quillier, Jean Georges (Saint-Etienne, FR) |
| Assignee: | Constructions Radioelectriques et Electroniques du Centre |
| Publication Number: | 3636371 |
| Application Number: | 04/849755 |
| Abstract: | A saw-tooth wave voltage generator comprises an integrator formed by a capacitor charged by means of an invariable current associated with a stable two-state tunnel-diode triggering circuit. One of the states of the diode controls return of the saw-tooth wave voltage to a starting reference level by means of a control amplifier which includes a comparator stage to which is applied the reference voltage and the output voltage of the generator, and the other state of the tunnel-diode releases operation of the generator. A second control amplifier interconnected with the first one and which takes its input voltage from the comparator stage of the latter functions to detect arrival of the saw-tooth wave voltage near the value of the reference voltage and applies it to the triggering circuit to control the biasing of the tunnel diode. |
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| Patent Number: |
3,533,008
|
| Title: | Push-pull Tunnel Diode Amplifier |
| Family: | Patent family and legal status for 3,533,008 |
| INPADOC Status: | Expired |
| Inventor(s): | Lee, Chong W. |
| Assignee: | GEN ELECTRIC |
| Publication Number: | 3533008 |
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| Patent Number: |
3,254,276
|
| Title: | Solid-state Translating Device With Barrier-layers Formed By Thin Metal And Semiconductor Material |
| Family: | Patent family and legal status for 3,254,276 |
| INPADOC Status: | Expired |
| Inventor(s): | Schwarz, Ruth F.; Spratt, James P. |
| Assignee: | PHILCO CORP |
| Publication Number: | 3254276 |
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| Patent Number: |
3,197,839
|
| Title: | Method Of Fabricating Semiconductor Devices |
| Family: | Patent family and legal status for 3,197,839 |
| INPADOC Status: | Expired |
| Inventor(s): | Tiemann, Jerome J. |
| Assignee: | GEN ELECTRIC |
| Publication Number: | 3197839 |
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| Patent Number: |
3,065,432
|
| Title: | Wide Range Tunnel Diode Oscillator |
| Family: | Patent family and legal status for 3,065,432 |
| INPADOC Status: | Expired |
| Inventor(s): | Duncan, Vigil D. |
| Assignee: | CAPITOL BROADCASTING COMPANY I |
| Publication Number: | 3065432 |
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| Patent Number: |
JPS 5990978A
|
| Title: | Superlattice Negative Resistance Element |
| Family: | Patent family and legal status for JPS 5990978A |
| INPADOC Status: | Unknown |
| Inventor(s): | Yanase Tomoo; Rangu Hiroyoshi |
| Publication Number: | JPS5990978 |
| Application Number: | JP19820200572 |
| Abstract: | PURPOSE:To obtain the negative resistance element with superlattice structure, through which the large degree of amplification is acquired, by flowing resonant tunnel currents through sections among a plural pair of levels and obtaining larger differential negative resistance. CONSTITUTION:The position 31 of the lower end of a conductive band changes in a sine wave shape in the direction 39 vertical to the upper surface 38 of a substrate 37. GaAs is used as a substrate mixed crystal, and a mixed crystal layer consists of Ga1-xAlxAs. The change of the sine wave shape is obtained by altering a composition ratio (x) of Al in a sine wave shape. When the shape of a potential well formed by the spatial change of the position of the lower end of the conductive band takes a sine wave, scattered energy levels 33, 34, 35, 36 are arranged at approximately regular intervals. When voltage is applied to the superlattice, regions 44 in which a field drop focuses are generated. When applied voltage is increased to a proper value, the energy levels of the left potential wells and those of the right potential wells coincide in a plurality of pairs while holding the thin-film regions 44, the resonant tunnel currents 41, 42, 43 flow through three pairs of the levels, and large differential negative resistance is obtained. |
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| Patent Number: |
JPS 5967676A
|
| Title: | Super Lattice Negative Resistance Element |
| Family: | Patent family and legal status for JPS 5967676A |
| INPADOC Status: | Unknown |
| Inventor(s): | Yanase Tomoo; Rangu Hiroyoshi |
| Publication Number: | JPS5967676 |
| Application Number: | JP19820178827 |
| Abstract: | PURPOSE:To obtain a large amplification degree by a method wherein thin film layers of different forbidden band widths are formed alternately, and a thin film of a smaller forbidden band width is so formed that the lower end shape of a conduction band becomes parabolic. CONSTITUTION:In layers 31 sandwiched by layers 32 of larger forbidden band widths, the position of the lower ends of the conduction layer thereof varies in a direction vertical to a thin film surface and in parabolic form projected downward. If the shape of a potential well of the conduction band is on the parabola, discrete energy levels are shown to be at equal intervals by quantum mechanics. Thus, a region 42 with the concentration of field drops generates. When an impressed voltage is increased up to a suitable value, the energy level of the left side layer and that of the right side with the thin film region 42 placed therebetween are coincident by a plurality of pairs (four pairs in this case), and accordingly resonant tunnel current 41 flows through the four pairs of levels. Therefore, a large differential negative resistance can be obtained. |
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| Patent Number: |
GB 2107927A
|
| Title: | Avalanche Photodiode With Quantum Well Layer |
| Family: | Patent family and legal status for GB 2107927A |
| INPADOC Status: | Expired -PATENT CEASED THROUGH NON-PAYMENT OF RENEWAL FEE Effective DATE 20011007 |
| Inventor(s): | Matsushima Yuichi; Sakai Kazuo; Kushiro Yukitoshi; Akiba Shigeyuki; Noda Yukio; Utaka Katsukuki |
| Publication Number: | GB2107927 |
| Application Number: | GB19820028721 |
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| Patent Number: |
GB 1084565A
|
| Title: | Transistor Switching Circuit |
| Family: | Patent family and legal status for GB 1084565A |
| INPADOC Status: | Unknown |
| Publication Number: | GB1084565 |
| Application Number: | GB19650012278 |
| Abstract: | 1,084,565. Switching circuits oscillators. GENERAL ELECTRIC CO. March 23, 1965 [April 6, 1964], No. 12278/65. Heading H3T. [Also in Division H2] An oscillator or switching circuit comprises a saturable transformer with one winding connected between base and emitter of a transistor across which is also a tunnel diode connected in like polarity to the base-emitter junction. In Fig. 4, consider the transistor 11 to be cut off and the transformer core 16 to be in negative saturation. Resistors 24, 25 will apply a small bias to the transistor and to tunnel diode 33 so that a small current will flow through each. A small collector current will flow through winding 15 and bring the core out of saturation, inducing a voltage across winding 18 positive at the dot end. This voltage increases regeneratively and eventually switches the tunnel diode to its high-voltage region and turns on the transistor fully to supply current to the load 17. When the core reaches positive saturation the voltage across winding 18 falls to zero and the current through resistors 53, 54 applies a bias to the transistor to turn it off. Diode 41 prevents this bias from being shorted by the tunnel diode. The collapse of current through winding 15 unsaturates the core and induces a voltage in winding 18 that is positive at the no-dot end, thus reverting the tunnel diode to its lowvoltage state. Diode 55 (which may be connected as shown dotted) protects the emitterbase junction from this reverse voltage. Diode 44 prevents impedance mismatch between the tunnel diode and the transistor. A voltage applied to the base of transistor 57 will control the point at which the core reaches positive saturation and hence the conduction period of transistor 11. Similarly a voltage applied to the base of transistor 59 will turn off transistor 11 instantly in case of possible damage. Further control windings can be added if desired. In a modification (Fig. 8, not shown) the regenerative back-coupling to the transformer is omitted and switching is effected by a square-wave signal continuously applied to a winding on the transformer. A further control winding switched by transistor 57 is also provided. In Fig. 9 this principle is applied to the control of a bridge inverter supplying either A.C. or D.C. to a load. Fig. 9 shows one half of the bridge, the other half being identical and the load being connected between the arrows on the two halves (Fig. 10, not shown). The saturable transformer is split into two, 16 and 16<SP>1</SP>, operating on alternate half-cycles of the square-wave signal applied to windings 15, 15<SP>1</SP>. The same signal is rectified at 64a and used as reverse bias for ensuring turn off of the transistor 1 1a. As the value of the voltage on the base of transistor 57 increases, the conducting period of transistor 11a falls from 360 degrees to zero. The rate of switching is twice the frequency of the square-wave signal. As in Fig. 4, multiple control inputs can be provided. The switching currents flow through pulse transformers 71, 72 which apply gating signals to SCR's 73, 74 connected to a similar tunnel diode and power transistor circuit 33b and 11b. When each SCR is turned on, a pulse of current is supplied from the same square-wave source 62 to the transistor 11b, which is provided with a reverse-bias circuit 64b identical to that of transistor 11a. The transistors 11a and 11b are arranged to conduct alternately, and the similar circuit forming the other half of the bridge is switched in synchronism so that current flows to the load through two power transistors in series (Fig. 10, not shown). |
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| Patent Number: |
EP 0034166A1
|
| Title: | Semiconductor Embedded Layer Technology |
| Family: | Patent family and legal status for EP 0034166A1 |
| INPADOC Status: | Expired -LAPSED IN A CONTRACTING STATE ANNOUNCED VIA POSTGRANT INFORM. FROM NAT. OFFICE TO EPO Ref Country Code DE Effective DATE 19930501 |
| Inventor(s): | Bozler Carl O; Alley Gary D; Lindley William T; Murphy R Allen |
| Publication Number: | EP0034166 |
| Application Number: | EP19800901688 |
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